A known method relates to diffusion soldered connections, used for producing a thermally stable connection via diffusion joining. For this purpose, a first body is coated with a high-melting metal and a second body is coated with a low-melting metal. Then the two bodies can be joined at a given temperature and a given contact pressure via a diffusion soldered connection. High-melting intermetallic phases thereby form, the melting points of which are higher than the melting point of the low-melting metal. With the known joining method, individual joining locations of an electronic power device can be produced in a thermally stable manner.
However, an electronic power semiconductor device has a number of joining locations, which are created by multistage methods. For this purpose, another known method relates to the multistage production of diffusion soldered connections for power semiconductor devices with semiconductor chips. For this purpose, diffusion joining of a rear side of a semiconductor chip to a chip island of a substrate is established by a first diffusion joint and diffusion joining of an upper side of a semiconductor chip to wiring patterns of a further substrate is established by a further diffusion joint, the diffusion joints having different melting temperatures on account of different intermetallic phases that are formed.
In the case of the known diffusion soldering methods, often an excess of low-melting joining components, such as tin, is used, while the high-melting components, such as gold and/or palladium, are given in exact volumes. Such diffusion soldering methods have the disadvantage that excess low-melting joining components put at risk the reliability and heat resistance of the diffusion joints. Another risk is that the intermetallic phases extend so far in the diffusion joint that the ductility of the diffusion joint is reduced and the brittleness predominates in an inadmissible way, such that there is an increased risk of damage, in particular the development of microcracks, under exposure to changing temperatures, with an increase in the transfer resistance of the diffusion joint.
A conventional method for the planar joining of a rear side of a power semiconductor chip to a large-area rear-side electrode of a semiconductor chip island which has a copper heat sink is shown by FIG. 9. Firstly, the surface 4 of the copper heat sink, as a substrate or base component 1 of a semiconductor device, is cleaned in first cleaning positions 14 and 15 at an elevated temperature by reduction in a reducing atmosphere 3 of forming gas with 5% by volume of hydrogen, the remainder nitrogen. In a joining material coating position 16, a wire 19 of joining material is lowered onto the upper side 4 of the copper heat sink, and a joining material melt 20 is applied while wetting the upper side.
The joining material melt 20 is reduced in a further heating position 17 and fed to a joining position 18. In the joining position 18, a power semiconductor chip is lowered onto the joining material melt 20 as the component 2 to be joined. The joining material melt 20 is thereby deformed into a virtually rectangular base area while wetting the metallization on the rear side of the chip. The power semiconductor chip is kept adjusted until the liquid metal phases and alloys have cooled and solidified under interdiffusion and alloy formation between the joining material melt and the material of the copper heat sink and also between the joining material melt and the metallization on the rear side of the chip.
This known way of conducting the process according to FIG. 9 has the following disadvantages and risks.
1. An oxidation of the metal melt in the time between the melting process and the lowering of the power semiconductor chip leads to wetting problems;
2. An inadequate joining material thickness under the corners and edges of the chip as a result of poor positioning of the solder material wetting and non-adapted form of the solder melt leads to reliability risks;
3. A tilting of the chip by a sea of melt leads to process problems in subsequent wire bonding processes, in particular with regard to adjustment and contact area detection, which likewise entails reliability risks;
4. Voids in the joining joint reduce the thermal conductivity and limit the electrical energy that can be handled or switched in a power semiconductor device. Such voids are produced by two previously known effects:
a—wetting defects at the boundary surfaces of the upper side of the heat sink to the joining material and the joining material to the rear side of the power semiconductor chip; and
b—creation of voids during lengthy thermal exposure of the joining joint on account of phase growth and increases in the size of crystalline grains; and
5. A strongly pressed-out joining material limits the size of the semiconductor chip or the size of the contact terminal area for special packages, since the joining material extends beyond the sides to be joined.